Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification

Using Design-Level Scan to Improve Design Observability and Controllability for Functional Verification of FPGAs

Scan Cell Design for Enhanced Delay Fault Testability

This paper addresses problems in testing scannable sequential circuits for delay faults. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A lay-out on a gate array has been designed and evaluated for this scan cell.

Scan Design and Secure Chip

Testing a secure system is often considered as a severe bottleneck. While testability requires to an increase in both observability and controllability, secure chips are designed with the reverse in mind, limiting access to chip content and on-chip controllability functions. As a result, using usual design for testability techniques when designing secure ICs may seriously decrease the level of ...

OCCOM: Efficient Computation of Observability-Based Code Coverage Met&

Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it is not computationally feasible to exhaustively simulate designs. It is important therefore to quantitatively measure the degree of verification coverage of the design. Coverage metrics proposed for measuring the extent o...

Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST

This paper proposes a new testability analysis and test-point insertion method at the register transfer level (RTL), assuming a full scan and a pseudorandom built-in self-test design environment. The method is based on analyzing the RTL synchronous specification in synthesizable very high speed integrated circuit hardware descriptive language (VHDL). A VHDL intermediate form representation is f...